The present invention relates to a multilayer wiring board and a method for manufacturing the same and a probe apparatus using the multilayer wiring board.
Semiconductor ICs such as semiconductor chips are collectively formed on a semiconductor wafer and undergo an electrical test before being separated into respective chips. For this electrical test, a probe apparatus connected to electrode pads of each semiconductor IC as a device under test is used in general. Respective probes of the probe apparatus contact the corresponding electrode pads of the device under test to cause the device under test to be connected to a tester for the electrical test (for example, refer to Patent Document 1).
In such a probe apparatus, a multilayer wiring board is used as a probe board, and numerous probes are arranged on one surface of the probe board. Also, in wiring circuits built in this probe board or multilayer wiring board, electrical resistive elements are built for the purpose of electrical matching such as impedance matching.
A method for building the resistive elements in the multilayer wiring board is proposed in Patent Document 2, for example. With the method described in Patent Document 2, in relation to a manufacturing process of a multilayer wiring board having an insulating substrate and a multilayer wiring layer provided on the insulating substrate, a titanium nitride film functioning as a foundation layer for wires and functioning as resistive elements is formed on the multilayer wiring layer, and wires are formed on the titanium nitride film by a conductor such as copper, thus to enable efficient building of the resistive elements in the multilayer wiring board.
Meanwhile, in the multilayer wiring layer of the multilayer wiring board, a lower-layer conductive layer formed on the insulating substrate and an upper-layer conductive layer piled on the lower-layer conductive layer via an intermediate insulating layer are connected, for example. For this connection between the both conductive layers, a via hole penetrating the intermediate insulating layer in the thickness direction is formed, and the lower-layer conductive layer and the upper-layer conductive layer are electrically connected through a via deposited in the via hole. When a metal material for this via is deposited in the via hole, the metal material for the via partially rises at the rim portion of the via hole. Thus, when an upper-layer insulating film is formed to cover the upper-layer conductive layer connected to the lower-layer conductive layer through the via, convexo-concave corresponding to the rise of the via is formed on this upper-layer insulating film.
When the aforementioned resistive elements are formed on this convexo-concave upper-layer insulating film by deposition of their material, these resistive elements are formed in a waved shape in the up-down direction along the convexo-concave surface of the aforementioned upper-layer insulating film. Accordingly, the substantial length of each resistive element increases, and the thickness dimension of the resistive element tends to change partially, as a result of which there is a disadvantage of increase in an error of a value of each resistive element built in the multilayer wiring board.
(Patent Document 1) Japanese Patent Appln. Public Disclosure No. 2005-17121; (Patent Document 2) Japanese Patent Appln. Public Disclosure No. 2000-13016